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LT3092 1 3092p typical application description 200ma 2-terminal programmable current source the lt ? 3092 is a programmable 2-terminal current source. it requires only two resistors to set an output current between 0.5ma and 200ma. a multitude of analog techniques lend themselves to actively programming the output current. the LT3092 is stable without input and output capacitors, offering high dc and ac impedance. this feature allows operation in intrinsically safe applications. the set pin features 1% initial accuracy and low tem- perature coef? cient. current regulation is better than 10ppm/v from 1.5v to 40v. the LT3092 can operate in a 2-terminal current source con? guration in series with signal lines. it is ideal for driv- ing sensors, remote supplies, and as a precision current limiter for local supplies. internal protection circuitry includes reverse-battery and reverse-current protection, current limiting and thermal limiting. the LT3092 is offered in the 8-lead tsot-23, 3-lead sot-223 and 8-lead 3mm 3mm dfn packages. adjustable 2-terminal current source features applications n programmable 2-terminal current source n maximum output current: 200ma n wide input voltage range: 1.2v to 40v n input/output capacitors not required n resistor ratio sets output current n initial set pin current accuracy: 1% n reverse-voltage protection n reverse-current protection n <1mv load regulation typical n <0.001%/v line regulation typical n current limit and thermal shutdown protection n available in 8-lead sot-23, 3-lead sot-223 and 8-lead 3mm 3mm dfn packages n 2-terminal floating current source n gnd referred current source n variable current source n in-line limiter n intrinsic safety circuits set pin current vs temperature 3092 ta01a in set out + C LT3092 10a r out r set v in C v out = 1.2v to 40v ia r r source set out = 10 ? temperature (c) C50 9.900 set pin current (a) 9.950 10.000 10.050 C25 0 25 50 100 75 125 10.100 9.925 9.975 10.025 10.075 150 3092 ta01b l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. electrical specifications subject to change
LT3092 2 3092p pin configuration absolute maximum ratings in pin voltage relative to set, out ........................40v set pin current (note 6) .....................................15ma set pin voltage (relative to out, note 6) ...............10v output short-circuit duration .......................... inde? nite (note 1) all voltages relative to v out top view dd package 8-lead (3mm s 3mm) plastic dfn 5 6 7 8 9 4 3 2 1 out out nc set in in nc nc t jmax = 125c, ja = 28c/w, jc = 10c/w exposed pad (pin 9) is out, must be soldered to out on the pcb. see the applications information section. 3 2 1 top view tab is out in out set st package 3-lead plastic sot-223 t jmax = 125c, ja = 24c/w, jc = 15c/w tab is out, must be soldered to out on the pcb. see the applications information section. nc 1 out 2 out 3 out 4 8 in 7 in 6 nc 5 set top view ts8 package 8-lead plastic tsot-23 t jmax = 125c, ja = 57c/w, jc = 15c/w order information lead free finish tape and reel part marking* package description temperature range LT3092edd#pbf LT3092edd#trpbf lfjd 8-lead (3mm 3mm) plastic dfn C40c to 125c LT3092idd#pbf LT3092idd#trpbf lfjd 8-lead (3mm 3mm) plastic dfn C40c to 125c LT3092est#pbf LT3092est#trpbf 3092 3-lead plastic sot-223 C40c to 125c LT3092ist#pbf LT3092ist#trpbf 3092 3-lead plastic sot-223 C40c to 125c LT3092mpst#pbf LT3092mpst#trpbf 3092mp 3-lead plastic sot-223 C55c to 125c LT3092ets8#pbf LT3092ets8#trpbf ltfjd 8-lead plastic sot-23 C40c to 125c LT3092its8#pbf LT3092its8#trpbf ltfjd 8-lead plastic sot-23 C40c to 125c lead based finish tape and reel part marking* package description temperature range LT3092edd LT3092edd#tr lfjd 8-lead (3mm 3mm) plastic dfn C40c to 125c LT3092idd LT3092idd#tr lfjd 8-lead (3mm 3mm) plastic dfn C40c to 125c LT3092est LT3092est#tr 3092 3-lead plastic sot-223 C40c to 125c LT3092ist LT3092ist#tr 3092 3-lead plastic sot-223 C40c to 125c LT3092mpst LT3092mpst#tr 3092mp 3-lead plastic sot-223 C55c to 125c LT3092ets8 LT3092ets8#tr ltfjd 8-lead plastic sot-23 C40c to 125c LT3092its8 LT3092its8#tr ltfjd 8-lead plastic sot-23 C40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ operating junction temperature range (notes 2, 8) e, i grades ......................................... C40c to 125c mp grade ........................................... C55c to 125c storage temperature range ................... C65c to 150c lead temperature (st, ts8 packages only) soldering, 10 sec .............................................. 300c
LT3092 3 3092p electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: unless otherwise speci? ed, all voltages are with respect to v out . the LT3092e is tested and speci? ed under pulse load conditions such that t j ? t a . the LT3092e is 100% tested at t a = 25c. performance at C40c and 125c is assured by design, characterization, and correlation with statistical process controls. the LT3092i is guaranteed to meet all data sheet speci? cations over the full C40c to 125c operating junction temperature range. the LT3092mp is 100% tested and guaranteed over the C55c to 125c operating junction temperature range. note 3: minimum load current is equivalent to the quiescent current of the part. since all quiescent and drive current is delivered to the output of the part, the minimum load current is the minimum current required to maintain regulation. parameter conditions min typ max units set pin current i set v in = 2v, i load = 1ma 2v v in 40v, 1ma i load 200ma l 9.9 9.8 10 10 10.1 10.2 a a offset voltage (v out C v set ) v os v in = 2v, i load = 1ma v in = 2v, i load = 1ma l C2 C3.5 2 3.5 mv mv current regulation (note 7) i set v os i load = 1ma to 200ma i load = 1ma to 200ma l C0.1 C0.5 C2 na mv line regulation i set v os v in = 2v to 40v, i load = 1ma v in = 2v to 40v, i load = 1ma 0.03 0.003 0.2 0.010 na/v mv/v minimum load current (note 3) 2v v in 40v l 300 500 a dropout voltage (note 4) i load = 10ma i load = 200ma l l 1.22 1.3 1.45 1.6 v v current limit v in = 5v, v set = 0v, v out = C0.1v l 200 300 ma reference current rms output noise (note 5) 10hz f 100khz 0.7 na rms ripple rejection f = 120hz, v ripple = 0.5v p-p , i load = 0.1a, c set = 0.1f, c out = 2.2f f = 10khz f = 1mhz 90 75 20 db db db thermal regulation i set 10ms pulse 0.003 %/ w the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t j = 25c. (note 2) note 4: for the LT3092, dropout is speci? ed as the minimum input-to- output voltage differential required supplying a given output current. note 5: adding a small capacitor across the reference current resistor lowers output noise. adding this capacitor bypasses the resistor shot noise and reference current noise (see the applications information section). note 6: diodes with series 1k resistors clamp the set pin to the out pin. these diodes and resistors only carry current under transient overloads. note 7: current regulation is kelvin-sensed at the package. note 8: this ic includes overtemperature protection that protects the device during momentary overload conditions. junction temperature exceeds the maximum operating junction temperature when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability.
LT3092 4 3092p temperature (c) C50 C2.0 offset voltage (mv) C1.0 0.0 1.0 C25 0 25 50 100 75 125 2.0 C1.5 C0.5 0.5 1.5 150 3092 g03 input-to-output voltage (v) 0 C1.00 offset voltage (mv) C0.50 0 0.50 5 10 15 20 30 25 35 1.00 C0.75 C0.25 0.25 0.75 40 3092 g05 i out = 1ma temperature (c) C50 9.900 set pin current (a) 9.925 9.975 10.000 10.025 10.100 10.075 0 50 75 3092 g01 9.950 10.050 C25 25 100 125 150 set pin current distribution (a) 10.20 3092 g02 9.90 10 10.10 9.80 n = 1326 v os distribution (mv) 2 3092 g04 C1 0 1 C2 n = 1326 load current (ma) 0 C400 offset voltage (v) C350 C250 C200 C150 100 C50 100 3092 g06 C300 0 50 C100 50 150 200 typical performance characteristics offset voltage distribution offset voltage offset voltage current regulation set pin current set pin current distribution offset voltage (v out C v set ) temperature ( o c) C50 C80 change in reference current with load (na) C70 C50 C40 C30 20 C10 0 50 75 3092 g07 C60 0 10 C20 C25 25 100 125 150 i out = 1ma to 200ma v in C v out = 3v
LT3092 5 3092p temperature (c) C50 0 minimum output current (a) 200 300 400 600 0 50 75 3092 g08 100 500 C25 25 100 125 150 load current (ma) 0 0 dropout voltage (v in C v out ) (v) 0.4 0.8 1.2 25 50 75 100 150 125 175 1.6 0.2 0.6 1.0 1.4 200 3092 g09 t j = C55c t j = 25c t j = 125c temperature (c) C50 0 dropout voltage (v in C v out ) (v) 0.4 0.6 0.8 1.4 1.2 0 50 75 3092 g10 0.2 1.0 C25 25 100 125 150 i load = 100ma i load = 200ma input-to-output differential voltage (v) 0 0 current limit (ma) 100 200 300 2 4 6810 400 50 150 250 350 3092 g11 t j = 25c temperature (c) C50 0 current limit (ma) 50 150 200 250 500 350 0 50 75 3092 g12 100 400 450 300 C25 25 100 125 150 v in = 7v v out = 0v typical performance characteristics current limit line transient response line transient response dropout voltage dropout voltage current limit minimum output current time (s) 0 3092 g13 0 input voltage (v) output current deviation (ma) 8 20 40 60 4 6 C1.0 0 C0.5 0.5 1.0 1.5 2 10 30 80 100 50 70 90 1ma current source configuration time (s) 10 3092 g14 0 input voltage (v) output current deviation (ma) 8 20 40 60 4 6 C10 0 C5 5 10 2 10 30 80 100 50 70 90 10ma current source configuration
LT3092 6 3092p r test () 0 output voltage (mv) 800 700 600 500 400 300 200 100 0 3092 g17 2000 1000 v in = 36v v in = 5v set pin = 0v v in v out r test frequency (hz) 0.01 reference current noise spectral density (pa/ hz ) 100 10k 100k 100 10 1k 3092 g19 1 0.1 10 typical performance characteristics residual output for less than minimum output current output impedance noise spectral density turn-on response turn-on response frequency (hz) output impedance () 100 1k 10k 100k 1m 10m 10 100 1k 100m 10m 10 1 1g 100k 10k 1m 3092 g18 i source = 100ma i source = 10ma i source = 1ma time (s) 8 3092 g15 0 input voltage (v) output current (ma) 6 10 20 30 2 4 0 0.5 1.0 0 5 15 40 50 25 35 45 1ma current source configuration time (s) 8 3092 g16 0 input voltage (v) output current (ma) 6 10 20 30 2 4 0 5 10 15 0 5 15 40 50 25 35 45 10ma current source configuration
LT3092 7 3092p pin functions (dd/st/ts8) in (pins 7, 8/pin 3/pins 7, 8): input. this pin supplies power to bias internal circuitry and supply output load current. for the device to operate properly and regulate, the voltage on this pin must be 1.2v to 1.3v above the out pin (depending on output load currentsee the dropout voltage speci? cations in the electrical charac- teristics table). nc (pins 3, 5, 6/na/pins 1, 6): no connection. these pins have no connection to internal circuitry and may be tied to in, out, gnd or ? oated. out (pins 1, 2/pin 2/pins 2, 3, 4): output. this is the power output of the device. the LT3092 requires a 0.5ma minimum load current or the output will not regulate. set (pin 4/pin 1/pin 5): set. this pin is the error ampli- ? ers noninverting input and also sets the operating bias point of the circuit. a ? xed 10a current source ? ows out of this pin. two resistors program i out as a function of the resistor ratio relative to 10a. output current range is 0.5ma to the maximum rated 200ma level. exposed pad/tab (pin 9/tab/na): output. the exposed pad of the dfn package and the tab of the sot-223 package are tied internally to out. tie them directly to the out pins (pins 1, 2/pin 2) at the pcb. the amount of copper area and planes connected to out determine the effective thermal resistance of the packages. block diagram in set out 10a 3092 bd C +
LT3092 8 3092p introduction the LT3092 is a versatile ic that operates as a 2-terminal programmable current source with the addition of only two external resistors; no external bypass capacitors are needed for stability. the LT3092 is easy to use and has all the protection fea- tures expected in high performance products. included are reverse-voltage protection, reverse-current protec- tion, short-circuit protection and thermal shutdown with hysteresis. the LT3092 operates with or without input and output capacitors. the simplest current source application requires only two discrete resistors to set a constant output current up to 200ma. a variety of analog tech- niques lend themselves to regulating and varying the current source value. the device utilizes a precision 0 tc 10a reference cur- rent source to program output current. this 10a current source connects to the noninverting input of a power operational ampli? er. the power operational ampli? er provides a low impedance buffered output of the voltage on the noninverting input. many application areas exist in which operation without input and output capacitors is advantageous. a few of these applications include sensitive circuits that cannot endure surge currents under fault or overload conditions and intrinsic safety applications in which safety regulations limit energy storage devices that may spark or arc. programming output current in 2 -terminal current source mode setting the LT3092 to operate as a 2-terminal current source is a simple matter. the 10a reference current from the set pin is used with one resistor to generate a small voltage, usually in the range of 100mv to 1v (200mv is a level that will help reject offset voltage, line regulation, and other errors without being excessively large). this voltage is then applied across a second resistor that connects from out to the ? rst resistor. figure 1 shows connections and formulas to calculate a basic current source con? guration. applications information with a 10a current source generating the reference that gains up to set output current, leakage paths to or from the set pin can create errors in the reference and output currents. high quality insulation should be used (e.g., te? on, kel-f). the cleaning of all insulating surfaces to remove ? uxes and other residues may be required. surface coating may be necessary to provide a moisture barrier in high humidity environments. minimize board leakage by encircling the set pin and circuitry with a guard ring operated at a potential close to itself; tie the guard ring to the out pin. guarding both sides of the circuit board is required. bulk leakage reduction depends on the guard ring width. ten nano- amperes of leakage into or out of the set pin and its as- sociated circuitry creates a 0.1% reference current error. leakages of this magnitude, coupled with other sources of leakage, can cause signi? cant offset voltage and refer- ence current drift, especially over the possible operating temperature range. figure 1. using the LT3092 as a current source ima var i v r a out set set out set out = == 05 10 10 . ? ? r r r set out in set out + C LT3092 10a i out v set r set 3092 f01 + C r out selecting r set and r out in figure 1, both resistors r set and r out program the value of the output current. the question now arises: the ratio of these resistors is known, but what value should each resistor be? the ? rst resistor to select is r set . the value selected should generate enough voltage to minimize the error caused by the offset between the set and out pins. a reasonable starting level is 200mv of voltage across r set (r set equal to 20k). resultant errors due to offset voltage are a few percent. the lower the voltage across r set becomes, the higher the error term due to the offset.
LT3092 9 3092p applications information inductive components and may be complex distributed networks. in addition, the current sources value will dif- fer between applications and its connection may be gnd referenced, power supply referenced or ? oating in a signal line path. linear technology strongly recommends that stability be tested in situ for any LT3092 application. in LT3092 applications with long wires or pcb traces, the inductive reactance may cause instability. in some cases, adding series resistance to the input and output lines (as shown in figure 2) may suf? ciently dampen these possible high-q lines and provide stability. the user must evaluate the required resistor values against the designs headroom constraints. in general, operation at low output current levels (< 5ma) automatically requires higher values of programming resistors and may provide the necessary damping without additional series impedance. if the line impedances in series with the LT3092 are complex enough such that series damping resistors are not suf? cient, a frequency compensation network may be necessary. several options may be considered. from this point, selecting r out is easy, as it is a straight- forward calculation from r set . take note, however, resistor errors must be accounted for as well. while larger voltage drops across r set minimize the error due to offset, they also increase the required operating headroom. obtaining the best temperature coef? cient does not require the use of expensive resistors with low ppm temperature coef? cients. instead, since the output current of the LT3092 is determined by the ratio of r set to r out , those resistors should have matching temperature characteristics. less expensive resistors made from the same material will provide matching temperature coef? cients. see resistor manufacturers data sheets for more details. stability and frequency compensation the LT3092 does not require input or output capacitors for stability in many current-source applications. clean, tight pcb layouts provide a low reactance, well controlled operating environment for the LT3092 without requiring capacitors to frequency-compensate the circuit. the data sheets front page typical application circuit illustrates the simplicity of using the LT3092. some current source applications will use a capacitor connected in parallel with the set pin resistor to lower the current sources noise. this capacitor also provides a soft-start function for the current source. this capacitor connection is depicted in figure 7 (see the quieting the noise section). when operating with a capacitor across the set pin resis- tor, external compensation is usually required to maintain stability and compensate for the introduced pole. the following paragraphs discuss methods for stabilizing the LT3092 for either this capacitance or other complex impedances that may be presented to the device. linear technology strongly recommends testing stability in situ with ? nal components before beginning production. although the LT3092s design strives to be stable without any capacitors over a wide variety of operating conditions, it is not possible to test for all possible combinations of input and output impedances that the LT3092 will encounter. these impedances may include resistive, capacitive and figure 2. adding series resistor decouples and dampens long line reactances in set out + C LT3092 10a r set r out r series r series long line reactance/inductance 3092 f02 long line reactance/inductance
LT3092 10 3092p applications information figure 3 depicts the simplest frequency compensation network as a single capacitor connected across the two terminals of the current source. in this case, either a capacitor with a value less than 1000pf, or greater than 1uf (esr < 0.5), may stabilize the circuit. some ap- plications may use the small value capacitor to stand off dc voltage, but allow the transfer of data down a signal line. for some applications, this capacitance range may be unacceptable or present a design constraint. one circuit example typifying this is an intrinsically-safe circuit in which an overload or fault condition potentially allows the capacitors stored energy to create a spark or arc. for applications in which a single capacitor is unacceptable, figure 3 alternately shows a series rc network connected across the two terminals of the current source. this network has two bene? ts. first, it limits the potential discharge current of the capacitor under a fault condition, preventing sparks or arcs. second, it bridges the gap between the upper bound of 1000pf for small capacitors to the lower bound of 1f for large capacitors such that almost any value capacitor can be used. this allows the user greater ? exibility for frequency compensating the loop and ? ne tuning the rc network for complex impedance networks. in many instances, a series rc network is the best solution for stabilizing the application circuit. typical resistor values will range from 100 to about 5k, especially for capacitor figure 4. input and/or output capacitors may be used for compensation values in between 1000pf and 1f. once again, linear technology strongly recommends testing stability in situ for any LT3092 application across all operating conditions, especially ones that present complex impedance networks at the input and output of the current source. if an application refers the bottom of the LT3092 current source to gnd, it may be necessary to bypass the top of the current source with a capacitor to gnd. in some cases, this capacitor may already exist and no additional capacitance is required. for example, if the LT3092 was used as a variable current source on the output of a power supply, the output bypass capacitance would suf? ce to provide LT3092 stability. other applications may require the addition of a bypass capacitor. once again, the same capacitor value requirements previously mentioned apply in that an upper bound of 1000pf exists for small values of capacitance, and a lower bound of 1f (esr < 0.5) exists for large value capacitors. a series rc network may also be used as necessary, and depends on the application requirements. in some extreme cases, capacitors or series rc networks may be required on both the LT3092s input and output to stabilize the circuit. figure 4 depicts a general application using input and output capacitor networks, rather than an input-to-output capacitor. as the input of the current source tends to be high impedance, placing a capacitor on the input does not have the same effect as placing a 3092 f04 in set out + C LT3092 10a i out r set r out c out or v in c out r out c in r in figure 3. compensation across from input to output of current source provides stability 3092 f03 in set out + C LT3092 10a c comp or r set r out r comp c comp
LT3092 11 3092p applications information capacitor on the lower impedance output, and the same restrictions do not apply. capacitors in the range of 0.1f to 1f usually provide suf? cient bypassing on the input, and the value of input capacitance may be increased without limit. if an application uses gnd referred capacitors on the input or output (particularly the input), pay attention to the length of the lines powering and returning ground from the circuit. in the case where long power supply and return lines are coupled with low esr input capacitors, application-speci? c voltage spikes, oscillations and reliability concerns may be seen. this is not an issue with LT3092 stability, but rather the low esr capacitor forming a high-q resonant tank circuit with the inductance of the input wires. adding series resistance with the input of the LT3092, or with the input capacitor, often solves this. resistor values of 0.1 to 1 are often suf? cient to dampen this resonance. give extra consideration to the use of ceramic capacitors. ceramic capacitors are manufactured with a variety of di- electrics, each with different behavior across temperature and applied voltage. the most common dielectrics used are speci? ed with eia temperature characteristic codes of z5u, y5v, x5r and x7r. the z5u and y5v dielectrics are good for providing high capacitances in a small package, but they tend to have strong voltage and temperature coef? cients as shown in figures 5 and 6. when used with a 5v regulator, a 16v 10f y5v capacitor can exhibit an effective value as low as 1f to 2f for the dc bias voltage applied and over the operating temperature range. the x5r and x7r dielectrics result in more stable characteristics and are more suitable for use as the output capacitor. the x7r type has better stability across temperature, while the x5r is less expensive and is available in higher values. care still must be exercised when using x5r and x7r capacitors; the x5r and x7r codes only specify operating temperature range and maximum capacitance change over temperature. capacitance change due to dc bias with x5r and x7r capacitors is better than y5v and z5u capacitors, but can still be signi? cant enough to drop capacitor values below appropriate levels. capacitor dc bias characteristics tend to improve as component case size increases, but expected capacitance at operating voltage should be veri? ed. voltage and temperature coef? cients are not the only sources of problems. some ceramic capacitors have a piezoelectric response. a piezoelectric device generates voltage across its terminals due to mechanical stress. in a ceramic capacitor the stress can be induced by vibrations in the system or thermal transients. dc bias voltage (v) change in value (%) 3092 f05 20 0 C20 C40 C60 C80 C100 0 4 8 10 26 12 14 x5r y5v 16 both capacitors are 16v, 1210 case size, 10f figure 5. ceramic capacitor dc bias characteristics temperature (c) C50 40 20 0 C20 C40 C60 C80 C100 25 75 3092 f06 C25 0 50 100 125 y5v change in value (%) x5r both capacitors are 16v, 1210 case size, 10f figure 6. ceramic capacitor temperature characteristics
LT3092 12 3092p applications information quieting the noise when a reduction in the noise of the current source is desired, a small capacitor can be placed across r set (c set in figure 7). normally, the 10a reference current source generates noise current levels of 2.7pa/ hz (0.7na rms over the 10hz to 100khz bandwidth). the set pin resistor generates a spot noise equal to i n = 4kt/r (k = boltzmanns constant, 1.38 ? 10 C23 j/k, and t is absolute temperature) which is rms-summed with the noise generated by the 10a reference current source. placing a c set capacitor across r set (as shown in figure 7) bypasses this noise current. note that this noise reduction capacitor increases start-up time as a factor of the time constant formed by r set ? c set . when using a capacitor across the set pin resistor, the external pole introduced usually requires compensation to maintain stability. see the stability and frequency compensation section for detailed descriptions on compensating LT3092 circuits. a curve in the typical performance characteristics section depicts noise spectral density for the reference current over a 10hz to 100khz bandwidth. paralleling devices obtain higher output current by paralleling multiple LT3092s together. the simplest application is to run two current sources side by side and tie their inputs together and their outputs together, as shown in figure 8. this allows the sum of the current sources to deliver more output current than a single device is capable of delivering. another method of paralleling devices requires fewer components and helps to share power between devices. tie the individual set pins together and tie the individual in pins together. connect the outputs in common using small pieces of pc trace as ballast resistors to promote equal current sharing. pc trace resistance in milliohms/ inch is shown in table 1. ballasting requires only a tiny area on the pcb. table 1. pc board trace resistance weight (oz) 10mil width 20mil width 1 54.3 27.1 2 27.1 13.6 trace resistance is measured in m/in the worst-case offset, only 2mv between the set pin and the out pin, allows the use of very small ballast resistors. as shown in figure 9, each LT3092 has a small 40m ballast resistor, which at full output current gives better than 80% equalized sharing of the current. the external resistance of 40m (20m for the two devices in paral- lel) only adds about 8mv of output voltage compliance at an output of 0.4a. of course, paralleling more than two LT3092s yields even higher output current. spreading the device on the pc board also spreads the heat. series input resistors can further spread the heat if the input-to-output difference is high. thermal considerations the LT3092s internal power and thermal limiting circuitry protects itself under overload conditions. for continuous normal load conditions, do not exceed the 125c maximum junction temperature. carefully consider all sources of thermal resistance from junction-to-ambient. this includes (but is not limited to) junction-to-case, case-to-heat sink interface, heat sink resistance or circuit board-to-ambient figure 7. adding c set lowers current noise 3092 f07 in set out + C LT3092 10a c comp or r set r out r comp c comp c set
LT3092 13 3092p applications information as the application dictates. consider all additional, adjacent heat generating sources in proximity on the pcb. surface mount packages provide the necessary heat sinking by using the heat spreading capabilities of the pc board, copper traces and planes. surface mount heat sinks, plated through-holes and solder ? lled vias can also spread the heat generated by power devices. junction-to-case thermal resistance is speci? ed from the ic junction to the bottom of the case directly, or the bottom of the pin most directly, in the heat path. this is the lowest thermal resistance path for heat ? ow. only proper device mounting ensures the best possible thermal ? ow from this area of the package to the heat sinking material. note that the exposed pad of the dfn package and the tab of the sot-223 package are electrically connected to the output (v out ). the following tables list thermal resistance as a function of copper areas in a ? xed board size. all measurements were taken in still air on a four-layer fr-4 board with 1oz solid internal planes and 2oz external trace planes with a total ? nished board thickness of 1.6mm. pcb layers, copper weight, board layout and thermal vias affect the resultant thermal resistance. although tables 2 through 4 provide thermal resistance numbers for four-layer boards with 1oz internal and 2oz external copper, modern multilayer pcbs can provide slightly bet- figure 8. connect two LT3092s for higher current figure 9. parallel devices 3092 f08 1.33 1.33 300 300 i out i out , 300ma + C LT3092 10a 10a + C LT3092 20k 20k in in set set out out out out 3092 f09 i out i out , 400ma + C LT3092 10a + C LT3092 10a r 2.5 r x 50k 40m* 40m* *40m pc board trace 1v in in set set r vr x in max = () ? % 90
LT3092 14 3092p ter performance than found in these tables. demo circuit 1531as board layout using multiple inner v out planes and multiple thermal vias achieves tbdc/w performance for the dfn package. table 2. dd package, 8-lead dfn copper area thermal resistance (junction-to-ambient) topside* backside board area 2500mm 2 2500mm 2 2500mm 2 tbdc/w 1000mm 2 2500mm 2 2500mm 2 tbdc/w 225mm 2 2500mm 2 2500mm 2 tbdc/w 100mm 2 2500mm 2 2500mm 2 tbdc/w *device is mounted on topside table 3. ts8 package, 8-lead sot-23 copper area thermal resistance (junction-to-ambient) topside* backside board area 2500mm 2 2500mm 2 2500mm 2 tbdc/w 1000mm 2 2500mm 2 2500mm 2 tbdc/w 225mm 2 2500mm 2 2500mm 2 tbdc/w 100mm 2 2500mm 2 2500mm 2 tbdc/w *device is mounted on topside table 4. st package, 3-lead sot-223 copper area thermal resistance (junction-to-ambient) topside* backside board area 2500mm 2 2500mm 2 2500mm 2 tbdc/w 1000mm 2 2500mm 2 2500mm 2 tbdc/w 225mm 2 2500mm 2 2500mm 2 tbdc/w 100mm 2 2500mm 2 2500mm 2 tbdc/w *device is mounted on topside for further information on thermal resistance and using thermal information, refer to jedec standard jesd51, notably jesd51-12. calculating junction temperature example: given an industrial factory application with an input voltage of 15v 10%, an output voltage of 12v 5%, an output current of 200ma and a maximum ambient temperature of 50c, what would be the maximum junc- tion temperature for a dfn package? the total circuit power equals: p total = (v in C v out )(i out ) the set pin current is negligible and can be ignored. v in(max continuous) = 16.5 (15v + 10%) v out(min continuous) = 11.4v (12v C 5%) i out = 200ma power dissipation under these conditions equals: p total = (16.5 C 11.4v)(200ma) = 1.02w junction temperature equals: t j = t a + p total ? ja t j = 50c + (1.02w ? 60c/w) = 111.2c in this example, the junction temperature is below the maximum rating, ensuring reliable operation. protection features the LT3092 incorporates several protection features ideal for battery-powered circuits, among other applications. in addition to normal circuit protection features such as current limiting and thermal limiting, the LT3092 protects itself against reverse-input voltages, reverse-output volt- ages, and reverse out-to-set pin voltages. current limit protection and thermal overload protection protect the ic against output current overload condi- tions. for normal operation, do not exceed a junction temperature of 125c. the thermal shutdown circuits typical temperature threshold is 165c and has about 5c of hysteresis. the LT3092s in pin withstands 40v voltages with respect to the set and out pins. reverse-current ? ow, if out is greater than in, is less than 1ma (typically under 100a), protecting the LT3092 and sensitive loads. clamping diodes and 1k limiting resistors protect the LT3092s set pin relative to the out pin voltage. these protection components typically only carry current under transient overload conditions. these devices are sized to handle 10v differential voltages and 15ma crosspin current ? ow without concern. two immediate scenarios present themselves for these application concerns. the ? rst scenario employs a noise-reducing set pin bypass capacitor while out is instantaneously shorted to gnd. the second scenario follows improper shutdown techniques in which the set pin is quickly reset to gnd while out is held up by a large output capacitance with light load. applications information
LT3092 15 3092p typical applications paralleling LT3092s for higher current high voltage current source ia r r r r out =+ ? ? ? ? ? ? 10 2 1 4 3 ? 3092 ta02 in set out + C LT3092 10a r1 r2 in set out + C LT3092 10a r3 r4 i out 3092 ta03 in set out + C LT3092 10a r1 40m r2 40.2k in set out + C LT3092 10a r3 40m r4 2 400ma 3092 ta04 in set out + C LT3092 10a r3 2 r4 20k + C d1 35v i out 100ma in set out + C LT3092 10a r1 2 r2 20k 200mv d2 35v ima i mv r out out = 05 200 1 . 3092 ta05 in set out + C LT3092 10a r1 2 r x r2 20k i out 100ma vvv r v mv r max in out max x max = = (? ) ?% 200 1 90 paralleling current sources with ballast resistor decreasing power dissipation in LT3092 100ma current source 3092 ta06 in set out + C LT3092 10a r1 2 c1 r2 20k i out 100ma limit dv dt i c out 90 1 %? capacitor adds stability, but limits slew rate
LT3092 16 3092p typical applications 3092 ta07 in set out + C LT3092 10a i out v in load murata ncp15wf104f03rc 1% 100k 49.9k 49.9 3092 ta08 in set out + C LT3092 10a i out = 0.5ma to 100ma dac output 0v to 1v 10 3092 ta09 in set out + C LT3092 10a 1ma output input v + 100 10k 3092 ta11 in set out + C LT3092 10a 200ma v in opto-fet 100k 4.99 nec ps 7801-1a 3092 ta10 in set out + C LT3092 10a i out 200ma v in load vn2222ll 20k 1 on off pulsed current source, load to ground fully floating current source switches from 200ma to quiescent current dac controlled current source remote temperature sensor active load
LT3092 17 3092p typical applications 3092 ta12 in set 1 20k out + C LT3092 10a i out v in load on off + C LT3092 10a 3092 ta13 i out i set i out i out 20k r v i out 02 . pulsed current source, load to v in 2-terminal ac current limiter voltage clamp 3092 ta14 in set out + C LT3092 10a 10k 10k 10k v out v in v in C v out = 11v trip point 100k 10v 4.99 2n3906 2n3904 3092 ta15 in set out + C LT3092 10a 124 0.1% 10ma i out lt1634-1.25 high accuracy current source
LT3092 18 3092p package description dd package 8-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1698) 3.00 0.10 (4 sides) 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on top and bottom of package note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-1) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 0.38 0.10 bottom view?xposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 2.38 0.10 (2 sides) 1 4 8 5 pin 1 top mark (note 6) 0.200 ref 0.00 ?0.05 (dd) dfn 1203 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.675 0.05 3.5 0.05 package outline 0.25 0.05 0.50 bsc typical applications 3092 ta17 in set out + C LT3092 boost sw bias fb v in v in shdn lt3470a zvp3306f gnd 10a c3 47f 1 36v 1k 1nf i out 20k 100 0.22f 33h + C 3092 ta16 in set out + C LT3092 v in vn2222ll* 10a 4.99 *current foldback circuit limits the LT3092 power dissipation i out = 200ma, if v in C v out < 12v = 100ma, if v in C v out > 12v v out 100k* 10k* 100k 10v* 2-level current source more ef? cient current source
LT3092 19 3092p information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description .114 C .124 (2.90 C 3.15) .248 C .264 (6.30 C 6.71) .130 C .146 (3.30 C 3.71) .264 C .287 (6.70 C 7.30) .0905 (2.30) bsc .033 C .041 (0.84 C 1.04) .181 (4.60) bsc .024 C .033 (0.60 C 0.84) .071 (1.80) max 10 o max .012 (0.31) min .0008 C .0040 (0.0203 C 0.1016) 10 o C 16 o .010 C .014 (0.25 C 0.36) 10 o C 16 o recommended solder pad layout st3 (sot-233) 0502 .129 max .059 max .059 max .181 max .039 max .248 bsc .090 bsc 1.50 C 1.75 (note 4) 2.80 bsc 0.22 C 0.36 8 plcs (note 3 ) datum a 0.09 C 0.20 (note 3) ts8 tsot-23 0802 2.90 bsc (note 4) 0.65 bsc 1.95 bsc 0.80 C 0.90 1.00 max 0.01 C 0.10 0.20 bsc 0.30 C 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.52 max 0.65 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref st package 3-lead plastic sot-223 (reference ltc dwg # 05-08-1630) ts8 package 8-lead plastic tsot-23 (reference ltc dwg # 05-08-1637)
LT3092 20 3092p linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2009 lt 0709 ? printed in usa related parts part number description comments ldo lt1761 100ma, low noise ldo 300mv dropout voltage, low noise: 20v rms , v in = 1.8v to 20v, thinsot? package lt1762 150ma, low noise ldo 300mv dropout voltage, low noise: 20v rms , v in = 1.8v to 20v, ms8 package ltc1844 150ma, very low dropout ldo 80mv dropout voltage, low noise <30v rms , v in = 1.6v to 6.5v, stable with 1f output capacitors, thinsot package lt1962 300ma, low noise ldo 270mv dropout voltage, low noise: 20v rms , v in = 1.8v to 20v, ms8 package lt1964 200ma, low noise, negative ldo 340mv dropout voltage, low noise 30v rms , v in = C1.8v to C20v, thinsot package lt3008 20ma, 45v, 3a i q micropower ldo 280mv dropout voltage, low i q : 3a, v in = 2v to 45v, v out = 0.6v to 39.5v; thinsot and 2mm 2mm dfn-6 packages lt3009 20ma, 20v, 3a i q micropower ldo 280mv dropout voltage, low i q : 3a, v in = 1.6v to 20v, v out = 0.6v to 19.5v; thinsot and sc70 packages lt3020 100ma, low voltage vldo linear regulator v in : 0.9v to 10v, v out : 0.2v to 5v (min), v do = 0.15v, i q = 120a, noise: <250v rms , stable with 2.2f ceramic capacitors, dfn-8, ms8 packages ltc3025 300ma micropower vldo linear regulator v in = 0.9v to 5.5v, dropout voltage: 45mv, low noise 80v rms , low i q : 54a, 6-lead 2mm 2mm dfn package ltc3035 300ma vldo linear regulator with charge pump bias generator v in = 1.7v to 5.5v, v out : 0.4v to 3.6v, dropout voltage: 45mv, i q : 100a, 3mm 2mm dfn-8 lt3080/ lt3080-1 1.1a, parallelable, low noise, low dropout linear regulator 300mv dropout voltage (2-supply operation), low noise: 40v rms , v in : 1.2v to 36v, v out : 0v to 35.7v, current-based reference with 1-resistor v out set; directly parallelable (no op amp required), stable with ceramic caps, to-220, sot-223, msop-8 and 3mm 3mm dfn-8 packages; lt3080-1 version has integrated internal ballast resistor lt3085 500ma, parallelable, low noise, low dropout linear regulator 275mv dropout voltage (2-supply operation), low noise: 40v rms , v in : 1.2v to 36v, v out : 0v to 35.7v, current-based reference with 1-resistor v out set; directly parallelable (no op amp required), stable with ceramic caps, msop-8 and 2mm 3mm dfn-6 packages current sense ampli? ers lt6106 low cost, 36v high side current sense ampli? er 36v (44v max) current sense, dynamic range of 2000:1, 106db of psrr lt6107 high temperature high side current sense amp in sot-23 36v (44v max) current sense, dynamic range of 2000:1, 106db of psrr, C55 to 150c (mp-grade) thinsot is a trademark of linear technology corporation. current limiter for remote power 3092 ta19 in set out + C LT3092 10a 4.99 v out v in 100k adjust limit ldo typical applications usb led driver 3092 ta18 in set out + C LT3092 10a 1 200ma led usb 20k

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